1. Field of the Invention
The present invention relates to a semiconductor memory device, a method for manufacturing the same, a memory circuit, and a method for driving the same, and more particularly, to a single transistor cell, a method for manufacturing the same, a memory circuit composed of the single transistor cells, and a method for driving the memory circuit.
2. Description of the Related Art
A ferroelectric material is a dielectric material in which polarization generated by an external electric field remains partially after removing the external electric field, and the polarization direction can be changed by changing the direction of the external electric field.
Memory devices manufactured using a ferroelectric thin film may be categorized into two types.
The first type of device is a destructive read out (DRO) type memory device, which means that when data is read out, the data is lost from the memory and must be written again. The device is constituted with a capacitor which is manufactured using a ferroelectric thin film dielectric, and a transistor which is used to read or write signals of two directions stored in the capacitor. Here, the memory device is commonly called a ferroelectric random access memory (FRAM), and the driving principle thereof is similar to a dynamic random access memory (DRAM). However, unlike the DRAM, the FRAM requires no refresh and is a non-volatile memory which keeps stored information even when the power supply is turned off.
The second type of device is a non-destructive read out (NDRO) ferroelectric memory device which reads stored information without destruction, unlike the DRO memory device. The device is obtained by forming a ferroelectric capacitor on the gate electrode of a transistor, and operates by determining whether a channel exists in a silicon surface under a gate oxide layer along a polarization direction of the ferroelectric capacitor. For instance, it is recognized that if a channel exists, 1 is written, and if not, 0 is written.
A memory cell including only a single transistor without a capacitor, unlike the DRAM or FRAM, would be advantageous for integration, but would require an access for selecting a cell or a selection transistor in order to perform random access.
No method for exactly realizing an array of cells each formed of only one transistor of an NDRO type has been disclosed. However, a similar SFRAM is disclosed in U.S. Pat. No. 5,070,385 xe2x80x9cFerroelectric non-volatile variable resistive elementxe2x80x9d by Evans, Jr., Joseph T. and Bullington, Jeff A.
FIG. 1 is a sectional view of a conventional SFRAM, disclosed in the above patent.
In FIG. 1, reference numeral 10 indicates a gate, which is actually part of, a word line, reference numeral 12 indicates a ferroelectric layer, reference numeral 14 indicates a channel region, reference numeral 16 indicates a drain, reference numeral 18 indicates a source, reference numeral 20 indicates an interdielectric layer, reference numeral 22 indicates a first metal electrode, and reference numeral 24 indicates a second metal electrode.
The SFRAM of FIG. 1 is a thin film transistor (TFT). The word line 10 is formed on a semiconductor substrate (not shown), and the ferroelectric layer 12 is formed on the word line 10. Here, an oxide layer (not shown) is interposed between the word line 10 and the semiconductor substrate. The drain 16 is formed on a left semiconductor layer around the word line 10, and the source 18 is formed on the right semiconductor layer. The channel region 14 is formed between the drain 16 and the source 18 above the word line 10.
When a predetermined voltage is applied to the word line 10, the spontaneous polarization is induced in the ferroelectric layer 12, and thus a conductive channel is formed or not formed in the channel region 14.
For instance, if the source and drain are doped with an N-type impurity, and by a drive method xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d is written to a cell transistor, then xe2x80x9c1xe2x80x9d indicates the state in which the conductive channel is formed in the channel region, and xe2x80x9c0xe2x80x9d indicates the state in which no conductive channel is formed. When a positive voltage (+V) is applied to the word line 10, N-type ions are accumulated in the channel region 14 due to the polarization of the ferroelectric layer 12, so that the conductive channel is formed, to thereby write xe2x80x9c1xe2x80x9d in the cell transistor. When a negative voltage (xe2x88x92V) is applied to the word line 10, P-type ions are accumulated in the channel region 14 due to the polarization of the ferro dielectric layer 12, so that a non-conductive channel is formed, to thereby write xe2x80x9c0xe2x80x9d in the cell transistor.
Meanwhile, in order to read the data stored in the cell transistor, if +V is applied to the second metal electrode 24 while the conductive channel is formed in the channel region 14, i.e., xe2x80x9c1xe2x80x9d is written, current passes through the first metal electrode 22, and if a non-conductive channel is formed in the channel region 14, i.e., xe2x80x9c0xe2x80x9d is written, current does not pass through the first metal electrode 22. Thus, the current passing through the first metal electrode 22 is measured, to thereby read the cell transistor of xe2x80x9c1xe2x80x9d or xe2x80x9c0xe2x80x9d.
In the conventional SFRAM, read and write are performed by normal drive of the unit cell. However, in order to read or write information in an arbitrary unit cell, each cell requires a further two access transistors, which prevents high integration density for the memory device.
It is an objective of the present invention to provide a single transistor cell including a unit cell formed of one transistor, capable of random access of the unit cell.
It is another objective of the present invention to provide a method of manufacturing the single transistor cell.
It is still another objective of the present invention to provide a memory circuit formed of single transistor cells, in which a unit cell is formed of one transistor, and which can randomly access the unit cells.
It is yet another objective of the present invention to provide a method for driving the memory circuit.
Accordingly, to achieve the first objective, a single transistor cell according to the present invention comprises an island type semiconductor layer as an active region formed on a ferroelectric layer, a word line crossing the semiconductor layer, a source formed on the semiconductor layer one side of on the word line, and a drain formed on the semiconductor layer on the other side of the word line, a plate line formed below the ferroelectric layer to face the word line, intersecting the word line, a drive line connected to the source, and a bit line connected to the drain.
Here, the plate line is formed of platinum, and the ferroelectric line is formed of one selected from the group consisting of PZT, PLZT, PNZT, PbTiO3 and Y1, the semiconductor layer is formed of an oxide such as SnO2. The word line is formed of a material having a high work function, to reduce leakage current. Also, the word line is formed of either polysilicon doped with impurities or aluminum.
To achieve the second objective, a method for manufacturing a single transistor cell according to the present invention comprises (a) forming a rectangular plate line extending in a first direction, on a semiconductor substrate, (b) forming a rectangular ferroelectric line extending in a second direction perpendicular to the first direction to intersect the plate line, on the resultant structure where the plate line is formed, (c) forming an island type semiconductor layer on the ferroelectric line in a region where the ferroelectric line overlaps the plate line, and (d) forming a rectangular word line extending in the second direction to cross the semiconductor layer.
A reaction preventing layer is formed before forming the plate line, to suppress reaction of the semiconductor substrate with the ferroelectric line. The reaction preventing layer is formed of TiO2.
Forming the plate line comprises the substeps of depositing Pt on the entire surface of the semiconductor substrate, and photo etching the Pt to form the plate line extending in the first direction.
Forming the ferroelectric line comprises the substeps of depositing ferroelectric material on the entire surface of the resultant structure where the plate line is formed, by either a sol-gel coating method or a sputtering method, and photo etching the ferroelectric material to form the ferroelectric line, extending in the second direction perpendicular to the first direction and intersecting the plate line. The ferroelectric material is either PZT, PLZT, PNZT, PbTiO3 or Y1 .
Forming the semiconductor layer comprises the substeps of forming SnO2 on the entire surface of the resultant structure where the ferroelectric line is formed, implanting In ions into the SnO2 layer, and photo etching the In-implanted SnO2 layer to form an island type semiconductor layer in a region where the plate line overlaps the ferroelectric line. The semiconductor layer is formed of an oxide.
Forming the word line comprises the substeps of forming an oxide layer on the. entire surface of the substrate where a semiconductor layer is formed, forming a conductive material on the oxide layer, and photo etching the conductive material and the oxide layer to form the rectangular word line across the semiconductor layer.
After forming the word line, impurity ions are implanted on the entire surface of the substrate of the resultant structure where the word line is formed, to form a source and a drain on the semiconductor layer to the right and left of the word line, a first interdielectric layer is formed on the entire surface of the substrate where the source and drain are formed, the first interdielectric layer is selectively etched to form a first contact window partially exposing the source, a drive line is formed connected to the source through the first contact window, on the first interdielectric layer, a second interdielectric layer is formed on the entire surface of the substrate of the resultant structure where the drive line is formed, the first and second interdielectric layers are selectively etched to form a second contact window partially exposing the drain, and a bit line is formed connected to the drain through the second contact window, on the second interdielectric layer.
To achieve the third objective, in a memory circuit formed of single transistor cells according to the present invention, a source of a first cell transistor and a source of a second cell transistor are connected in common to a drive line, a drain of the first cell transistor is connected to a first bit line, a drain of the second cell transistor is connected to a second bit line, a gate of the first cell transistor is connected to a first word line, a gate of the second cell transistor is connected to a second word line, and. ferroelectric layers of the first and second cell transistors are in connected in common to a plate line.
Here, the unit circuit shares the plate line with other unit circuits horizontally adjacent to the unit circuit, shares a drain of an odd-numbered horizontally adjacent cell transistor with the first bit line, a drain of an even-numbered horizontally adjacent cell transistor with the second bit line, shares the drive line with vertically adjacent unit circuits, shares the first word line with a gate of odd-numbered cell transistors of vertically adjacent unit circuits, and shares the second word line with a gate of even numbered cell transistors of vertically adjacent unit circuits.
To achieve the fourth objective, in a method for driving a memory circuit according to the present invention, in order to write xe2x80x9c1xe2x80x9d to an arbitrary cell, a voltage V is applied to a plate line connected to a ferroelectric layer, a word line connected to a gate of a cell transistor facing the ferroelectric layer is grounded, a drive line connected to a source of the cell transistor and a bit line connected to a drain of the cell transistor are floated. In order to write xe2x80x9c0xe2x80x9d to an arbitrary cell, a voltage V is applied to the plate line, a voltage V is applied to the word line, and the drive line and the bit line are floated. Here, a word line, a drive line and a bit line of a cell requiring no write, which shares a plate line with the arbitrary cell, are floated. In order to read data stored in an arbitrary cell, a voltage V is applied to the drive line and a current induced in the bit line is measured. Here, all drive lines except a drive line connected to a cell requiring read are floated, in order to read the data stored in an arbitrary cell.
If xe2x80x9c1xe2x80x9d is written to an arbitrary cell, a voltage xe2x88x92V is applied to the word line to increase the difference in electric potential between the word line and the plate line, and if xe2x80x9c0xe2x80x9d is written to an arbitrary cell, a voltage xe2x88x92V is applied to the plate line to increase the difference in electric potential between the word line and the plate line. Also, a voltage of ⅓ Vccxcx9cxc2xd Vcc is applied to the word line to increase an on-current of the cell.
Thus, the plate line intersects the word line, and the ferroelectric layer and the semiconductor layer are interposed between the plate line and the word line, so that information is written to or read from an arbitrary unit cell, and the drive line intersects the bit line, increasing a data sensing margin.